This invention relates to semiconductor memory devices and more particularly to an improved sense amplifier for an MOS random access dynamic read/write memory.
Dynamic MOS memory devices have heretofore used bistable differential sense amplifiers which have inputs connected to bit lines (column lines) which are split in two halves. Dummy cells establish a reference voltage on the unselected halves. Sense amplifiers of this type are shown in U.S. Pat. No. 4,239,993 issued to McAlexander, White and Rao, U.S. Pat. No. 4,081,701 issued to White, McAdams and Redwine, and U.S. Pat. No. 3,940,747, issued to Kuo and Kitagawa, all assigned to Texas Instruments.
The differential sense amplifiers previously used have required a period of time in the cycle for equallizing the bit line halves during precharge. This period has been 50 ns, for example, and when the goal is production of high speed devices this equallization time period becomes a significant factor.
It is the principal object of this invention to provide an improved sense amplifier for a high speed random access read/write memory, particularly for an array of one-transistor cells. Another object is to provide a sense amplifier which may be used in a dynamic memory array with reduced precharge time so the cycle time is short.